Yanbing Liu - Quality & Reliability Assurance Reliability Engineering, GLOBALFOUNDRIES, US, Inc

基本信息

Career Trajectory

Bio

Yang Liu was born in Hubei, China. He received the bachelor’s degree in electrical engineering from the University of Newcastle, Callaghan, NSW, Australia, in 2007. He was with Chartered Semiconductor, Singapore, from 2005 to 2012, where he was a Spice Modeling Engineer. Since 2012, he has been with GLOBALFOUNDRIES, Malta, NY, USA, as a Senior Engineer, focusing on reliability measurement solutions.

Research Interests

Papers共 11 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

Reliability of 2T-Core CMOS OTP Non-Volatile Memory Bitcells

R. Ranjan,T. Nigam,Y. Liu, A. Gondal,A. Kerber,M. I. Natarajan,B. Parameshwaran,J. Versaggi, E. Ehrichs

2017 IEEE International Reliability Physics Symposium (IRPS)（2017）

Cited0Views0EIWOSBibtex

Impact Of Ac Voltage Stress On Core Nmosfets Tddb In Finfet And Planar Technologies

R. Ranjan,Y. Liu,Tanya Nigam,A. Kerber,B. Parameshwaran

2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)（2017）

Cited12Views0EIWOSBibtex

(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies

X. He,D. H. Triyoso,S. Uppal,B. Fu,X. Zhang,S. Yamaguchi,C. Yong,B. Liu,M. Joshi,S. Samavedam

ECS Transactionsno. 1 (2017): 373-378

Cited0Views0Bibtex

Reliability-Performance Trade-Off For Work-Function Optimization In Advanced Node Replacement Metal Gate Technology

R. Ranjan,T. Nigam,B. Parameshwaran,Y. Liu, S. F. Yap

2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)（2016）

Cited9Views0EIWOSBibtex

Fast TDDB for early reliability monitoring

Charles LaRow,Y. Liu,Zakariae Chbili, A. Gondal

2016 IEEE International Integrated Reliability Workshop (IIRW)（2016）

Cited4Views0EIWOSBibtex

Advanced RMG Module to Improve AC/DC Performance for 14nm FinFETs and Beyond

M. Togo,M. Joshi,H. V. Meer,Y. Liu,C. Yong,B. Liu,X. He,X. Wu,S. Y. Mun,X. Zhang, D. Konduparthi, J. Lian,G. Bohra, W. H. Tong, C. Y. Xiao,D. Triyoso,E. Banghart,S. M. Pandey,A. Wei,R. Pal,R. Carter,M. H. Nam,M. Eller,S. Samavedam

2014 Symposium on VLSI Technology (VLSI-Technology) Digest of Technical Papers（2014）

Cited1Views0EIWOSBibtex

Anti-fuse Memory Array Embedded in 14nm FinFET CMOS with Novel Selector-Less Bit-Cell Featuring Self-Rectifying Characteristics

Y. Liu,M. H. Chi,A. Mittal,G. Aluri, S. Uppal,P. Paliwoda, E. Banghart,K. Korablev,B. Liu, M. Nam,M. Eller,S. Samavedam

2014 Symposium on VLSI Technology (VLSI-Technology) Digest of Technical Papers（2014）

Cited8Views0EIWOSBibtex

Impact of Hydrogen in Capping Layers on BTI Degradation and Recovery in High-Κ Replacement Metal Gate Transistors

M. Jin,C. E. Tian,G. La Rosa,S. Uppal,W. Mcmahon,H. Kothari,Y. Liu,E. Cartier,W. L. Lai,A. Dasgupta, S. Polvino,M. Belyansky,A. Chen, X. Zhou,A. Madan,Y. Yao,N. Klymko,V. Narayanan

Reliability Physics Symposium（2013）

Cited3Views0EIWOSBibtex

Process and local layout effect interaction on a high performance planar 20nm CMOS

Fumihiko Sato,Ravi P Ramachandran,H Van Meer,Kyung Hwa Cho, A Ozbek, Xiangdong Yang,Yanbing Liu, Zengxia Li,Xiaojie Wu, Supriya Jain,Henry K Utomo,Uihui Kwon, Yeongmin Park,W L Tan, Xiangguo Dai,W Lai,Jungho Kim, David R Jones,Michael P Ganz,Doo Hwan Bae,Rosine Lallement,Sri Charan Vemula, Taekyoung Kwon, Peng Lee, Yaoyao Qi,M Weybright,Andreas Scholze,R Bingert, J King,M Sherony,Michael A Eller,Huiling Shang,K Tabakman,Vijaykrishnan Narayanan,Srikanth B Samavedam,R Divakaruni

VLSI Circuits（2013）

Cited23Views0EIWOSBibtex

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